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WS1105 cdma cell 3x3 power amplifier module (824-849 mhz) data sheet description the WS1105 is a cdma(code division multiple access) power amplifier module designed for handsets operating in the 824-849mhz bandwidth. the WS1105 features coolpam circuit technology that offers state-of-the-art reliability, temperature stability and ruggedness. digital mode control of coolpam reduces current con- sumption, which enables extended talk time of mobile devices. the WS1105 meets stringent cdma linearity requirements to and beyond 28dbm output power. the 3mmx3mm form factor 8-pin surface mount package is self contained, incor- porating 50ohm input and output matching networks. functional block diagram features excellent linearity low quiescent current high efficiency C pae at 28dbm: 41.2% C pae at 16dbm: 17.7% 8-pin surface mounting package C 3mmx3mmx1.0mm internal 50ohm matching networks for both rf input and output rohs compliant applications digital cdma cellular wireless local loop output match input match inter stage match da pa bias circuit & control logic rf input (2) rf output (7) vcc1(1) vcc2(8) vref(4) vcont(3) module mmic free datasheet http:///
2 table 1. absolute maximum ratings [1] parameter symbol min nominal max unit rf input power pin C C 10.0 dbm dc supply voltage vcc 0 3.4 5.0 v reference voltage vref 0 2.85 3.3 v control voltage vcont 0 2.85 3.3 v storage temperature tstg -55 C +125 c table 2. recommended operating condition parameter symbol min nominal max unit dc supply voltage vcc 3.2 3.4 4.2 v dc reference voltage vref 2.75 2.85 2.95 v mode control voltage C high power mode C low power mode vcont vcont 0 2.0 0 2.85 0.5 3.0 v v operating frequency fo 824 849 mhz ambient temperature ta -30 25 85 c table 3. power range truth table power mode symbol vref vcont [2] range high power mode pr2 2.85 low ~ 28dbm low power mode pr1 2.85 high ~ 16dbm shut down mode C 0 C C notes: 1. no damage assuming only one parameter is set at limit at a time with all other parameters set at or below nominal value. 2. high (2.0C3.0v), low (0.0vC0.5v). free datasheet http:///
3 table 4. electrical characteristics for cdma mode (vcc=3.4v, vref=2.85v, t=25c, zin/zout=50ohm) characteristics symbol condition min. typ. max. unit operating frequency range f ? 824 C 849 mhz gain gain_hi high power mode, pout = 28 dbm 24 29.5 db gain_low low power mode, pout = 16 dbm 14 17.5 db power added efficiency pae_hi high power mode, pout = 28 dbm 36 41.2 % pae_ low low power mode, pout = 16 dbm 13.6 17.7 % total supply current icc_hi high power mode, pout = 28 dbm 450 515 ma icc_ low low power mode, pout = 16 dbm 65 85 ma quiescent current iq_hi high power mode 93 125 ma iq_ low low power mode 13 25 ma reference current iref_hi high power mode, pout = 28 dbm 27ma iref_low low power mode, pout = 16 dbm 38ma control current icont low power mode, pout = 16 dbm 0.2 1 ma total current in power-down mode ipd vref=0v 0.2 5 a adjacent channel power ratio 900 khz offset 1.98 mhz offset acpr1_hi acpr2_hi high power mode, pout = 28 dbm -55 -59 -47 -57 dbc dbc 900 khz offset 1.98 mhz offset acpr1_ low acpr2_ low low power mode, pout = 16 dbm -59 -66 -47 -57 dbc dbc harmonic suppression second third 2f0 3f0 high power mode, pout = 28 dbm -39 -56 -30 -40 dbc dbc input vswr vswr ? 2:1 2.5:1 stability (spurious output) s vswr 6:1, all phase -60 dbc noise power in rx band rxbn -136.5 -132 dbm/hz ruggedness ru no damage pout<28dbm, pin<10dbm, all phase high power mode 10:1 vswr free datasheet http:///
4 characteristics data (vcc=3.4v, vref=2.85v, t=25c, zin/zout=50ohm) figure 1. total current vs. output power figure 2. gain vs. output power figure 3. power added efficiency vs. output power figure 4. adjacent channel power ratio 1 vs. output power figure 5. adjacent channel power ratio 2 vs. output power 0 50 100 150 200 250 300 350 400 450 500 0 5 10 15 20 25 30 pout(dbm) current(ma) 0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 pout(dbm) pae(%) -85 -80 -75 -70 -65 -60 -55 -50 -45 0 5 10 15 20 25 30 pout(dbm) acpr2(dbc) 10 15 20 25 30 35 0 5 10 15 20 25 30 pout(dbm) gain(db) -75 -70 -65 -60 -55 -50 -45 -40 0 5 10 15 20 25 30 pout(dbm) acpr1(dbc) 824mhz 836.5mhz 849mhz 824mhz 836.5mhz 849mhz 824mhz 836.5mhz 849mhz 824mhz 836.5mhz 849mhz 824mhz 836.5mhz 849mhz free datasheet http:///
5 evaluation board description figure 6. evaluation board schematic figure 7. evaluation board assembly diagram 1 vcc1 2 rf in 3 vcont 4 vref vcc2 8 rf out 7 gnd 6 gnd 5 vref vcont rf in vcc1 vcc2 rf out c4 4.7uf c3 100pf c2 100pf c1 330pf c5 4.7uf r1 0ohm c1 c2 c3 r1 c4 c5 1105 pyyww aaaaa free datasheet http:///
6 figure 8. package dimensional drawing and pin descriptions (all dimensions are in millimeters) package dimensions and pin descriptions pin descriptions pin # name description 1 vcc1 supply voltage 2 rfin rf input 3 vcont control voltage 4 vref reference voltage 5 gnd ground 6 gnd ground 7 rf out rf output 8 vcc2 supply voltage top view side view 3 0.1 2 3 4 5 8 7 6 3 0.1 pin 1 mark 1 1.0 0.1 0.60 x-ray bottom view 2.80 1.40 3.0 0.40 0.80 0.40 1.40 0.7 1.20 r 0.10 0.15x45 0.40 pin 1 mark 1105 pyyww aaaaa manufacturing part number lot number p manufacturing info yy manufacturing year ww work week aaaaa assembly lot number figure 9. marking specifications free datasheet http:///
7 peripheral circuit in handset msm pa_r0 rf out output matching circuit rf in WS1105 c3 v batt +2.85v c5 c4 c1 c8 c7 c6 l1 c2 vcc2 vcc1 vcont gnd figure 10. peripheral circuit notes : C recommended voltage for vref is 2.85v C place c1 near to vref pin C place c3 and c4 close to pin 1 (vcc1) and pin 8 (vcc2). these capacitors can affect the rf performance C use 50 transmission line between pam and duplexer and make it as short as possible to reduce conduction loss C -type circuit topology is good to use for matching circuit between pa and duplexer free datasheet http:///
8 calibration calibration procedure is shown in figure 11. two cali- bration tables, high mode and low mode respectively, are required for cool pam, which is due to gain differ- ence in each mode. for continuous output power at the mode change points, the input power should be adjusted according to gain step during the mode change. offset value (difference between rising point and falling point) offset value, which is the difference between the rising point (output power where pa mode changes from low mode to high mode) and falling point (output power where pa mode changes from high mode to low mode), should be adopted to prevent system oscillation. 3 to 5 db is recommended for hysteresis. average current & talk time probability distribution function implies that what is important for longer talk time is the efficiency of low or medium power range rather than the efficiency at full power. WS1105 idle current is 13ma and operating current at 16dbm is 65ma at nominal condition. this pa with low current consumption prolongs talk time by no less than 30 minutes compared to other pas average current = (pdf x current)dp pou min max high mode tx agc low mode rising falling figure 11.calibration procedure rising falling high mode low mode pou gain figure 12. setting of offset between rising and falling power 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.50 4.00 4.50 5.00 -50 -40 -30 -20 -10 0 10 20 30 pa out(dbm) 0 100 200 300 500 400 600 700 digitally controlled pam conv. cool pam current (ma) pdf(%) cdg urban cdg suburban figure 13. cdma power distribution function free datasheet http:///
9 pcb design guidelines the recommended WS1105 pcb land pattern is shown in figure 14 and figure 15. the substrate is coated with solder mask between the i/o and conductive paddle to protect the gold pads from short circuit that is caused by solder bleeding/bridging. stencil design guidelines a properly designed solder screen or stencil is required to ensure optimum amount of solder paste is deposited onto the pcb pads. the recommended stencil layout is shown in figure 16. reducing the stencil opening can potentially generate more voids. on the other hand, stencil openings larger than 100% will lead to excessive solder paste smear or bridging across the i/o pads or conductive paddle to adjacent i/o pads. considering the fact that solder paste thickness will directly affect the quality of the solder joint, a good choice is to use laser cut stencil composed of 0.100mm(4mils) or 0.127mm(5mils) thick stainless steel which is capable of producing the required fine stencil outline. figure 15. solder mask opening figure 14. metallization figure 16. solder paste stencil aperture 0.1 0.25 0.6 0.4 0.8 0.3 mm on 0.5 mm pitch 0.8 0.5 0.7 0.55 1.4 1.325 0.4 0.6 0.5 0.8 1.05 1.1 free datasheet http:///
10 tape and reel information figure 17. tape and reel format C 3 mm x 3 mm. dimension list annote millimeter annote millimeter a0 3.400.10 p2 2.000.05 b0 3.400.10 p10 40.000.20 k0 1.350.10 e 1.750.10 d0 1.550.05 f 5.500.05 d1 1.600.10 w 12.000.30 p0 4.000.10 t 0.300.05 p1 8.000.10 p0 y y p2 (1) p10 (3) d0 xx p1 (2) d1 f (1) w a section x - x section y - y a0 k0 0.1 r 0.5 r 1.0 detail a t b0 1105 pyyww aaaaa f free datasheet http:///
11 reel drawing figure 18. plastic reel format (all dimensions are in millimeters) notes: 1. reel shall be labeled with the following information (as a minimum). a. manufacturers name or symbol b. avago technologies part number c. purchase order number d. date code e. quantity of units 2. a certi?cate of compliance (c of c) shall be issued and accompany each shipment of product. 3. reel must not be made with or contain ozone depleting materials. 4. all dimensions in millimeters (mm) 50 mi n . 1 2.4 + 2.0 - 0.0 1 8.4 ma x . 25 mi n wide ( ref ) s l o t for carrier t ape i n ser t io n for a tt ac h me nt t o ree l hu b ( 2 p l aces 1 80 apar t) bac k view f ron t view 1 78 s h adi n g i n dica t es th r u s l o t s + 0.4 - 0.2 2 1 .0 0.8 1 3.0 0.2 1 .5 mi n . free datasheet http:///
12 handling and storage esd (electrostatic discharge) electrostatic discharge occurs naturally in the environ- naturally in the environ- naturally in the environ- ment. with the increase in voltage potential, the outlet of neutralization or discharge will be sought. if the acquired discharge route is through a semiconductor device, de- through a semiconductor device, de- through a semiconductor device, de- de- de- structive damage will result. esd countermeasure methods should be developed and used to control potential esd damage during handling in a factory environment at each manufacturing site. msl (moisture sensitivity level) plastic encapsulated surface mount package is sensitive to damage induced by absorbed moisture and temperature. avago technologies follows jedec standard j-std 020b. each component and package type is classified for moisture sensitivity by soaking a known dry package at various temperatures and relative humidity, and times. after soak, the components are subjected to three con- secutive simulated reflows. the out of bag exposure time maximum limits are deter- mined by the classification test describe below which cor- responds to a msl classification level 6 to 1 according to the jedec standard ipc/jedec j-std-020b and j-std-033. WS1105 is msl3. thus, according to the j-std-033 p.11 the maximum manufacturers exposure time (met) for this part is 168 hours. after this time period, the part would need to be removed from the reel, de-taped and then re-baked. msl classification reflow temperature for the WS1105 is targeted at 260c +0/-5c. figure 19 and table 7 show typical smt profile for maximum temperature of 260 +0/-5c. table 5. esd classification pin # name description hbm cdm classification 1 vcc1 supply voltage 2000v 200v class 2 2 rfin rf input 2000v 200v class 2 3 vcont control voltage 2000v 200v class 2 4 vref reference voltage 2000v 200v class 2 5 gnd ground 2000v 200v class 2 6 gnd ground 2000v 200v class 2 7 rf out rf output 2000v 200v class 2 8 vcc2 supply voltage 2000v 200v class 2 note : 1. module products should be considered extremely esd sensitive table 6. moisture classification level and floor life msl level floor life (out of bag) at factory ambient =< 30c/60% rh or as stated 1 unlimited at =< 30c/85% rh 2 1 year 2a 4 weeks 3 168 hours 4 72 hours 5 48 hours 5a 24 hours 6 mandatory bake before use. after bake, must be reflowed within the time limit specified on the label note : 1. the msl level is marked on the msl label on each shipping bag. free datasheet http:///
13 time temperature tp t 25c to peak ts preheat t l t p ts max ts min t l critical zone t l to t p ramp up ramp down 25 figure 19. typical smt reflow profile for maximum temperature = 260 +0/-5c table 7. typical smt reflow profile for maximum temperature = 260 +0/ -5c profile feature sn-pb solder pb-free solder average ramp-up rate (tl to tp) 3c/sec max 3c /sec max preheat C temperature min (tsmin) C temperature max (tsmax) C time (min to max) (ts) 100c 150c 60-120 sec 150c 200c 60-180 sec tsmax to tl C ramp-up rate 3c/sec max time maintained above: C temperature (tl) C time (tl) 183c 60-150 sec 217c 60-150 sec peak temperature (tp) 240 +0/-5c 260 +0/-5c time within 5c of actual peak temperature (tp) 10-30 sec 20-40 sec ramp-down rate 6c/sec max 6c/sec max time 25c to peak temperature 6 min max. 8 min max. free datasheet http:///
14 storage condition packages described in this document must be stored in sealed moisture barrier, antistatic bags. shelf life in a sealed moisture barrier bag is 12 months at <40c and 90% relative humidity (rh) j-std-033 p.7. out-of-bag time duration after unpacking the device must be soldered to the pcb within 168 hours as listed in the j-std-020b p.11 with factory conditions <30c and 60% rh. baking it is not necessary to re-bake the part if both conditions (storage conditions and out-of bag conditions) have been satisfied. baking must be done if at least one of the con- ditions above have not been satisfied. the baking condi- tions are 125c for 12 hours j-std-033 p.8. caution tape and reel materials typically cannot be baked at the temperature described above. if out-of-bag exposure time is exceeded, parts must be baked for a longer time at low temperatures, or the parts must be de-reeled, de-taped, re-baked and then put back on tape and reel. (see moisture sensitive warning label on each shipping bag for information of baking). board rework component removal, rework and remount if a component is to be removed from the board, it is recommended that localized heating be used and the maximum body temperatures of any surface mount component on the board not exceed 200c. this method will minimize moisture related component damage. if any component temperature exceeds 200c, the board must be baked dry per 4-2 prior to rework and/or component removal. component temperatures shall be measured at the top center of the package body. any smd packages that have not exceeded their floor life can be exposed to a maximum body temperature as high as their specified maximum reflow temperature. removal for failure analysis not following the above requirements may cause moisture/reflow damage that could hinder or com- pletely prevent the determination of the original failure mechanism. baking of populated boards some smd packages and board materials are not able to withstand long duration bakes at 125c. examples of this are some fr-4 materials, which cannot withstand a 24 hr bake at 125c. batteries and electrolytic capacitors are also temperature sensitive. with component and board temperature restrictions in mind, choose a bake tem- perature from table 4-1 in j-std 033; then determine the appropriate bake duration based on the component to be removed. for additional considerations see ipc-7711 andipc-7721. derating due to factory environmental conditions factory floor life exposures for smd packages removed from the dry bags will be a function of the ambient envi- ronmental conditions. a safe, yet conservative, handling approach is to expose the smd packages only up to the maximum time limits for each moisture sensitivity level as shown in table 7. this approach, however, does not work if the factory humidity or temperature is greater than the testing conditions of 30c/60% rh. a solution for address- ing this problem is to derate the exposure times based on the knowledge of moisture diffusion in the component package materials ref. jesd22-a120). recommended equivalent total floor life exposures can be estimated for a range of humidities and temperatures based on the nominal plastic thickness for each device. table 9 lists equivalent derated floor lives for humidities ranging from 20-90% rh for three temperature, 20c, 25c, and 30c. this table is applicable to smds molded with novolac, biphenyl or multifunctional epoxy mold compounds. the following assumptions were used in calculating table 9: 1. activation energy for diffusion = 0.35ev (smallest known value). 2. for 60% rh, use diffusivity = 0.121exp ( -0.35ev/kt) mm2/s (this used smallest known diffusivity @ 30c). 3. for >60% rh, use diffusivity = 1.320exp ( -0.35ev/kt) mm2/s (this used largest known diffusivity @ 30c). free datasheet http:///
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2010 avago technologies. all rights reserved. av02-2616en - august 17, 2010 table 8. recommended equivalent total floor life (days) @ 20c, 25c & 30c for ics with novolac, biphenyl and multifunctional epoxies (reflow at same temperature at which the component was classified) maximum percent relative humidity package type and body thickness moisture sensitivity level 5% 10% 20% 30% 40% 50% 60% 70% 80% 90% body thickness 3.1 mm including pqfps >84 pin, plccs (square) all mqfps or all bgas 1 mm level 2a 60 78 103 41 53 69 33 42 57 28 36 47 10 14 19 7 10 13 6 8 10 30c 25c 20c level 3 10 13 17 9 11 14 8 10 13 7 9 12 7 9 12 5 7 10 4 6 8 4 5 7 30c 25c 20c level 4 5 6 8 4 5 7 4 5 7 4 5 7 3 5 7 3 4 6 3 3 5 2 3 4 2 3 4 30c 25c 20c level 5 4 5 7 3 5 7 3 4 6 2 4 5 2 3 5 2 3 4 2 2 3 1 2 2 1 2 3 30c 25c 20c level 5a 2 3 5 1 2 4 1 2 3 1 2 3 1 2 3 1 2 2 1 1 2 1 1 2 1 1 2 30c 25c 20c body 2.1 mm thickness <3.1 mm including plccs (rectangular) 18-32 pin soics (wide body) soics 20 pins, pqfps 80 pins level 2a 86 148 39 51 69 28 37 49 4 6 8 3 4 5 2 3 4 30c 25c 20c level 3 19 25 32 12 15 19 9 12 15 8 10 13 7 9 12 3 5 7 2 3 5 2 3 4 30c 25c 20c level 4 7 9 11 5 7 9 4 5 7 4 5 6 3 4 6 3 4 5 2 3 4 2 2 3 1 2 3 30c 25c 20c level 5 4 5 6 3 4 5 3 3 5 2 3 4 2 3 4 2 3 4 1 2 3 1 1 3 1 1 2 30c 25c 20c level 5a 2 2 3 1 2 2 1 2 2 1 2 2 1 2 2 1 2 2 1 1 2 0.5 1 2 0.5 1 1 30c 25c 20c body thickness <2.1 mm including soics <18 pin all tqfps, tsops or all bgas <1 mm body thickness level 2a 28 1 2 2 1 1 2 1 1 1 30c 25c 20c level 3 11 14 20 7 10 13 1 2 2 1 1 2 1 1 1 30c 25c 20c level 4 9 12 17 5 7 9 4 5 7 3 4 6 1 2 2 1 1 2 1 1 1 30c 25c 20c level 5 13 18 26 5 6 8 3 4 6 2 3 5 2 3 4 1 2 2 1 1 2 1 1 1 30c 25c 20c level 5a 10 13 18 3 5 6 2 3 4 1 2 3 1 2 2 1 2 2 1 1 2 1 1 2 0.5 1 1 30c 25c 20c free datasheet http:///

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